1. Field of the Invention
The present invention is generally directed to servo systems that include a variable frequency oscillator which can be characterized as being non-linear. More specifically it is directed to phase locked loops which have a non-linear voltage controlled oscillator provided in combination with a charge accumulator and a charge pump.
2. Description of the Prior Art
A known phase locked loop (PLL) system 100 is illustrated in FIG. 1. The PLL system 100 includes a phase comparator (detector) 10 which receives a self-clocking DATA signal from an asynchronous data source such as a disk drive for example. The comparator 10 supplies a frequency incrementing control signal FUP and a frequency decrementing control signal FDN to a charge pump 20. The charge pump 20 generates a pump current I.sub.P which flows in either a positive or negative direction depending on whether one or the other of the respective frequency incrementing/decrementing signals, FUP and FDN, is supplied. The pump current I.sub.P is generated as one or more fixed magnitude pulses 21 each having a pulse width P.sub.w equal to the time of application of either the FUP or FDN signals. Depending on which of the FUP and FDN signals is applied, the I.sub.P current pulses will either add charge into or withdraw charge out from a charge accumulating capacitor 30. The capacitor 30 has a predetermined capacitance C.sub.i. Charge accumulation in the capacitor 30 generates an integrated voltage V.sub.i =.SIGMA.I.sub.p P.sub.w /Ci which is applied to the input of a voltage controlled oscillator (VCO) 40. The VCO 40 produces a periodic CLOCK signal having a variable frequency F.sub.out which is a function of the input voltage V.sub.i. The CLOCK signal is fed back to one input of the phase comparator 10 while the DATA signal, which is generally aperiodic and is therefore of unknown phase and frequency, is supplied to another input of the phase comparator 10.
Although the DATA signal is generally aperiodic, it is self-clocking in the sense that it has a fundamental clocking frequency which can be derived by averaging over time. The PLL system 100 is designed to derive this fundamental clocking frequency and to lock on to the phase of the incoming DATA signal as well. The operation of the PLL system will be explained for the case where the CLOCK signal lags behind the DATA signal and then for the case where the CLOCK signal leads the DATA signal.
In situations where incoming edges of the DATA signal arrive before corresponding edges of the CLOCK signal (the CLOCK signal lags), the phase comparator 10 outputs the frequency incrementing signal FUP to the charge pump 20 and thereby causes the charge pump to inject the pump current I.sub.p into the integrating capacitor 30 so as to accumulate charge therein. The input voltage V.sub.i of the VCO 40 is incremented by the accumulated charge and in response, the VCO increases the speed of the CLOCK signal. The CLOCK frequency F.sub.out is incremented to a value greater than the fundamental clocking frequency of the DATA signal. The edges of the faster CLOCK signal then begin to catch up with the edges of the slower DATA signal. The output frequency F.sub.out drops back to the value of the fundamental clocking frequency as the CLOCK edges close in on the DATA signal edges. Once the CLOCK signal is substantially in phase with the DATA signal, the phase comparator 10 ceases to output the frequency incrementing signal FUP and the output frequency F.sub.out is held at a steady state value which is for practical purposes equal to the fundamental clocking frequency of the DATA signal.
For cases where the DATA signal edges lag behind the CLOCK signal edges, the phase comparator 10 outputs the frequency decrementing signal FDN thereby causing the capacitor 30 to discharge to reduce V.sub.i and the output of the VCO (the CLOCK signal) to slow down. This delays the CLOCK signal edges until the edges of the DATA signal catch up to and align with the CLOCK signal. The FDN control signal is shut off once phase alignment is obtained.
The speed at which the PLL system 100 comes into alignment with the incoming DATA signal is referred to as the slew rate. It is desirable to provide the PLL system 100 with as high a slew rate as possible. The slew rate is limited by a characteristic loop gain G.sub.LOOP of the PLL system which in turn, is set by the gain functions (transfer functions) of the charge pump 20 and the VCO 40. For most applications the loop gain G.sub.LOOP of the PLL system 100 is kept constant to prevent undesirable loop oscillations. Circuit designers often purposefully provide the charge pump 20 with a constant amplification gain, that is, they hold the magnitude of the pump current I.sub.p at a constant level. Typically, the charge pump 20 is designed as a digital circuit which delivers the pump current I.sub.p in the form of rectangular pulses 21. The magnitude of the input voltage V.sub.i is changed by modulating the pulse width P.sub.w of the pump current pulses 21.
FIG. 2 illustrates a characteristic curve K.sub.40 that may be used to describe the gain function of a voltage controlled oscillator such as the VCO 40 used in the circuit of FIG. 1. The gain function defines the relation between the output frequency F.sub.out and the input voltage V.sub.i. Due to various design constraints, the gain function K.sub.40 of the VCO 40 is typically non-linear. The gain function K.sub.40 is often characterized by a rapidly rising first portion beginning at a low end V.sub.1 of the VCO's input voltage range and by a second portion which slopes off to a generally flat plateau when the input voltage V.sub.i is increased toward a high end V2 of the input range.
The system loop gain G.sub.LOOP is in part a function of how quickly the output frequency F.sub.out changes relative to a variable phase difference.DELTA.t detected by the phase detector (comparator) 10. The phase difference.DELTA.t is the timing gap between corresponding edges of the CLOCK and DATA signals. A linear rate of frequency change relative to the rate of phase difference change dF.sub.out /d.DELTA.t is often required to keep the loop gain G.sub.LOOP constant. Since the voltage V.sub.i across the capacitor 30 rises linearly relative to the phase difference .DELTA.t (V.sub.i =I.sub.p..DELTA.t/C.sub.i where .DELTA.t is the time of application of the pump current I.sub.p), only the slope of the characteristic curve K.sub.40 is of concern. The loop gain of the PLL system 100 is therefore often defined as: EQU G.sub.LOOP =f(dF.sub.out /dV.sub.i)
The above definition reflects the concern of PLL system designers for the curvature (non-linearity) of the VCO's gain function curve K.sub.40. Generally it is desirable to force the characteristic curve K.sub.40 of the VCO to be as linear as possible. This can be done by modifying the design of the VCO to include for example a pre-compensation circuit (not shown) between the capacitor 30 and VCO 40. The pre-compensation circuit changes the input voltage V.sub.i so as to compensate for the non-linearity of the K.sub.40 curve. The operating range .DELTA.V.sub.i and .DELTA.F.sub.out of the PLL system is thereby widened. Such linearization attempts, however, tend to increase the overall cost of the PLL system dramatically because they require additional components that must be matched to the characteristics of the VCO and they introduce new delays into the loop which complicate the design of the PLL system. In other designs, the circuitry of the VCO 40 is kept simple to reduce cost and the PLL system is restricted to operating in a small portion .DELTA.V.sub.i of the VCO's characteristic curve K.sub.40. The restriction is imposed by designers in order to maintain a generally constant loop gain G.sub.LOOP But the restriction also limits the usefulness of the PLL system to a very small frequency range .DELTA.F.sub.out such as indicated in FIG. 2. The present invention takes a different approach which allows designers to expand the usable .DELTA.V.sub.i and .DELTA.F.sub.out ranges of servo systems while employing relatively simple, low cost VCO's.